Semiconductor devices are continuing to be scaled to smaller dimensions. This is producing an increase in the overall density and number of interconnects being fabricated on the semiconductor device which in turn is creating new integration problems with respect to interconnect resistance-capacitance (RC) coupling.
Decreasing the dimensions of the interconnects increases their resistance (R), and reducing the spacing between interconnects increases the capacitance (C) between them. Propagation delay, crosstalk noise, and power dissipation of the device circuitry due to RC coupling become significant at smaller device geometries, especially between interconnect lines on the same level. In an effort to overcome the problems associated with increasing capacitance, low dielectric constant (low-k) materials have been proposed as a replacement for conventional interlevel dielectric (ILD) films commonly used in semiconductor device fabrication.
Current methods for planarizing low-k dielectric materials, however, are problematic. Specifically when using chemical-mechanical polishing (CMP) processes. The structure of many low-k dielectric materials is such that they have been found to be mechanically weak or compressible. The horizontal and vertical stresses applied during CMP processing are such that low-k dielectric materials are often deformed or damaged by the polishing process. One consequence of this damage is the generation of particles and defects that adversely affect device yields. Accordingly, a need exists to develop alternatives that overcome the aforementioned problems when planarizing low-k dielectric materials.